Silicon dioxide is a regularly used insulating material in semiconductor processing in the fabrication of integrated circuitry. One particular class of silicon dioxides are those doped with at least one of phosphorus, boron and germanium. Examples include phosphosilicate glass (PSG), borosilicate glass (BSG) and borophosphosilicate glass (BPSG). Such materials might be utilized as fill material in trench isolation, as interlevel dielectrics, and as well as in many other applications. A typical manner of depositing such materials is by chemical vapor deposition (CVD), which includes atomic layer deposition. In one exemplary CVD process, silicon, dopant and oxidizing precursors are continuously fed to a deposition reactor under conditions effective to in situ deposit a doped silicon dioxide layer on a substrate received therein. Alternately by way of example only, a substantially undoped silicon dioxide layer can be formed first, followed by ion implanting or diffusion doping of the desired dopants therein.
A usual or typical goal in silicon dioxide layer depositions is to attain a conformal covering over the substrate. A substantially conformal deposition is characterized by a substantially constant deposition thickness over all of a substrate, including over the high elevation areas, the low elevation areas, and the interconnecting surfaces therebetween. However in many such processes, a non-conformal deposition occurs whereby more material tends to deposit on the higher elevation substrate features than on the lower or lowest elevation of gaps between features. This can lead to “bread loafing” and the ultimate occlusion of the gaps resulting in undesirable void formation within the gaps. Such can be overcome with doped silicon dioxides as described above by a high temperature anneal/reflow step whereby the doped silicon dioxide is substantially liquified, thereby flowing to fill the gaps. However, such is not always effective, adds additional processing steps, and may not be practical as device geometries continue to be decreased horizontally without a corresponding decrease in the vertical geometries of the circuitry.
While the invention was motivated in addressing the above issues and improving upon the above-described drawbacks, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification or the drawings) and in accordance with the doctrine of equivalents.